Currently, when manufacturing stacked or 3 D chips, a physical alignment process is used to align entire wafers. This can limit the number of good stacked chips that can be derived from the stacked wafers. This is due to the fact that the yielding parts would have to align spatially in order to get a functionally good stacked chip. Because individual chip alignment is not used, one cannot pick all of the good chips from one wafer and pair them up with all of the good chips from the other wafer (which would give you the maximum yield percentage). One also does not have the ability to stack parts based on power and perfomiance criteria. These issues are usually mitigated by putting a high yielding design on one of the stacked chips. This, however, limits the complexity of the design that can be placed on that chip.
It has been shown that the chips can be aligned by using magnetic forces. While this process works it has some disadvantages. Magnetic material must be used in the process. Additionally the magnetic force will only align the chips in the X and Y directions. It also does not guarantee good electrical connection because the magnetic force does not require well polished metal in order to work. Also while using the magnetic force to align the chips it is impossible to tell what direction to move the chip in order to get a stronger force.